xilinx - Implementation time : Global iteration

 

xilinx Implemetation 시, Global Iteration time 이 가장길다.

Clock 단에 (* clock_buffer_type="BUFR" *) 을 주면, Implementation시, 감소 효과를 볼수 있다.

 

BUFR  = Regional Clock Buffer 기능.

//    BUFR     : In order to incorporate this function into the design,
//   Verilog   : the following instance declaration needs to be placed
//  instance   : in the body of the design code.  The instance name
// declaration : (BUFR_inst) and/or the port declarations within the
//    code     : parenthesis may be changed to properly reference and
//             : connect this function to the design.  All inputs
//             : and outputs must be connected.

//  <-----Cut code below this line---->

   // BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
   //       Artix-7
   // Xilinx HDL Language Template, version 2016.1

   BUFR #(
      .BUFR_DIVIDE("BYPASS"),   // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
      .SIM_DEVICE("7SERIES")  // Must be set to "7SERIES"
   )
   BUFR_inst (
      .O(O),     // 1-bit output: Clock output port
      .CE(CE),   // 1-bit input: Active high, clock enable (Divided modes only)
      .CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
      .I(I)      // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
   );

   // End of BUFR_inst instantiation