xilinx - logic level name 보기

 

logic level name 보기 :

1. Go to 'Synthesis Settings'.

2. Change the '-flatten_hierarchy' to none.

3. Re-Synthesize the design. (This will the ensure the full path is available)

4. Open the synthesized design.

5. In the Tools Tab, goto Timing->Check Timing.

6. Select only the 'loop' option and press ok.

 

Resource 최적화 :

http://www.xilinx.com/support/answers/9417.html