indexed part-select (Verilog 2001 => +: )

 

logic [31: 0] a_vect;
logic [0 :31] b_vect;

logic [63: 0] dword;
integer sel;

a_vect[ 0 +: 8] // == a_vect[ 7 : 0]
a_vect[15 -: 8] // == a_vect[15 : 8]
b_vect[ 0 +: 8] // == b_vect[0 : 7]
b_vect[15 -: 8] // == b_vect[8 :15]

for(i=0;i<4;i=i+1)
    dword[8*sel +: 8] // variable part-select with fixed width

 

(i=0) => dword[7:0]

(i=1) => dword[15:8]

(i=2) => dword[23:16]

(i=3) => dword[31:24]

 

 

 

a_vect[x +: y] => [ x + y -1 : x ]

a_vect[x -: y] => [ x : x - y + 1 ]